The storage density of a semiconductor memory device as represented by a DRAM (Dynamic Random Access Memory) is increasing in recent years, and a high speed is also required. The increase of the storage density has so far been achieved mainly by downsizing of memory cells and increase of chip sizes. However, there is a certain physical limit to a reduction in the size of the memory cell, and the increase in the chip size decreases productivity and hinders a speed increase.
In order to substantially solve the above problems, there is proposed a method of using separate chips for the core section that is formed with memory cells and the interface section that is formed with a peripheral circuit of the memory cells (see Japanese Patent Application Laid-open No. 2004-327474). According to this method, a semiconductor memory device that has conventionally one chip is divided into plural chips. Therefore, the size of one chip can be decreased substantially. Consequently, according to this method, it is expected to be able to achieve a larger density while securing high productivity.
When the core section and the interface section are formed using separate chips, core chips can be manufactured in the memory process, and the interface chips can be manufactured in the logic process. In general, a transistor manufactured in the logic process can achieve higher-speed operation than a transistor manufactured in the memory process. Therefore, when the interface chip is manufactured in the logic process, the circuit of the interface chip section can be operated at a higher speed than that conventionally achieved. Accordingly, the semiconductor memory device can achieve high-speed operations. Furthermore, the operation voltage of the interface chip can be decreased to about 1V, thereby decreasing power consumption.
FIG. 19 is a schematic diagram of the structure of a conventional semiconductor storage device in which the core unit and interface unit are separate chips, and shows an example in which four core chips 21 to 24 are allocated to one interface chip 10.
As shown in FIG. 19, the core chips 21 to 24 are provided with core units 21a to 24a, as well as data input-output circuits 21b to 24b. The input-output circuits 21b to 24b are connected in common to the interface chip 10 via through-electrodes 21c to 24c that are provided through the core chips 21 to 24, respectively.
Therefore, when data are written to any of the core chips 21 to 24, write data are supplied from the interface chip 10 to the through-electrodes 21c to 24c, and these data are latched by any of the data input-output circuits 21b to 24b. Conversely, when data are read from any of the core chips 21 to 24, read data are supplied to the through-electrodes 21c to 24c from any one of the data input-output circuits 21b to 24b, and these data are latched by the interface chip 10.
However, since the through-electrodes 21c to 24c for connecting the core chips 21 to 24 with the interface chip 10 are shared by the core chips in the conventional semiconductor storage device shown in FIG. 19, the through-electrodes 21c to 24c are occupied by the data to be written to one core chip, or by the data to be read from one core chip. The through-electrodes are therefore utilized with low efficiency, and high-speed data transfer is difficult to perform.
This problem can be overcome by connecting the through-electrodes 21c to 24c to the interface chip 10 by a different route for each core chips 21 to 24 without short-circuiting. However, when this configuration is adopted, not only does the number of through-electrodes increase in relation to the number of core chips layered, but the position in which the through-electrodes are formed changes for each chip. It is therefore impossible to manufacture these core chips 21 to 24 using the same mask, and this configuration is impractical.
Stray capacitance also increases due to the common connection of the through-electrodes 21c to 24c, and prevents data transferring in high-speed. These problems also become more severe as the number of layered core chips is increased in order to increase the storage capacity.